Regviz

Allwinner /D1H /SMHC[0] /SMHC_DRV_DL

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Interpret as SMHC_DRV_DL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CMD_DRV_PH_SEL)CMD_DRV_PH_SEL 0 (DAT_DRV_PH_SEL)DAT_DRV_PH_SEL

Description

Drive Delay Control Register

Fields

CMD_DRV_PH_SEL

Command Drive Phase Select
DAT_DRV_PH_SEL

Data Drive Phase Select

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data